In a PoE system, DC voltage is supplied by the PSE over the same wire pairs that carry differential Ethernet data. Alternatively, the DC voltage can be transmitted over the spare wire pairs in a CAT-5 Ethernet cable, while the differential data is transmitted over data wire pairs in the same CAT-5 cable. Similarly, in a PoDL system, only one wire pair is used, and the DC voltage and differential data are transmitted over the same wire pair. Both the PSE and the PD have circuitry (e.g., transformers, inductors, capacitors) that separate out the AC (data) and DC voltage signals transmitted by the wires. The DC voltage powers all the PD components, and the data is processed by a PHY (physical layer component). The various standards are set out in IEEE 802.3 and are well known.
The IEEE standards require a low power handshaking routine prior to the full DC voltage being coupled to the wire pair(s) by the PSE. Such a handshaking routine may include a signature resistance test to determine if the PD presents approximately 25 kOhms at its input, signifying that it is PoE-compatible. If so, a low power classification test may then be performed to identify the power requirements of the PD. If the handshaking routine conveys that the PD is compatible with receiving a DC voltage and the PSE can supply the required power, the PSE supplies the DC voltage to the wires to fully power the PD. The DC voltage may be, for example, about 44 volts, although other voltages may be appropriate depending on the system.
Every time the system is powered up, the handshaking routine must be performed in the event that the PD has been replaced with a non-PoE or non-PoDL system.
The IEEE also specifies a minimum load current (a “maintain power signature”) that must be detected by the PSE in order for the PSE to continue to supply the full DC voltage to the PD. If the PD load current goes below the minimum threshold current, the PSE assumes the PD has been disconnected and terminates the DC voltage. The PD may also be required to present a certain minimum capacitance across the wires, which is periodically sensed by the PSE during normal operation, in order for the PSE to continue to supply the DC voltage.
Even if the PD remains connected but goes into a low power sleep mode, causing the minimum current level to not be met, the PSE discontinues the DC voltage and a new handshaking routine must be performed before the DC voltage is again applied. In some applications, the powering up time may be significant, especially if a large capacitor in the PD needs to be charged up before the PD can operate.
To ensure the correct polarity DC voltage is supplied to the PD load, the IEEE standards require a full bridge rectifier between the PD input and the PD load. A smoothing capacitor is typically connected across the output of the rectifier to smooth the DC voltage.
Even if the PD produces a current pulse above the “maintain power signature” (MPS) level within the required period, the current would still have to pass through the full bridge rectifier. In the event that the PD load went into a low power mode and the smoothing capacitor was fully charged up (which would commonly occur), any droop of the input DC voltage below the capacitor voltage would cause the full bridge rectifier to be reverse biased. Hence, the rectifier would block any PD current pulse. This would cause the PSE to miss the current pulse and shut off the DC voltage.
Therefore, what is needed is a PoE or PoDL type system where, if the PD goes into a low power mode and there is an input DC voltage droop (reverse biasing the full bridge rectifier), the PD can still supply a current pulse above the MPS threshold current so that the PSE does not terminate the DC voltage. This will allow a more rapid start up of the PD when the PD is to go into its fully operational mode.